What is Advanced Packaging and Epoxy Molding Compound?

Definition: Understanding the Foundation of Modern Semiconductor Packaging

Advanced packaging refers to cutting-edge technologies that integrate and reconfigure chips at the package level using advanced design methodologies and integration processes to significantly enhance system functional density. Often called High-Density Advanced Packaging (HDAP), this field represents the forefront of semiconductor packaging development and has become a focal point across the entire industry .

According to Yole Group, the global advanced packaging market is projected to reach approximately $80 billion by 2030, growing at a compound annual growth rate (CAGR) of 9.4%. This growth is driven primarily by the insatiable demand for AI accelerators, High-Bandwidth Memory (HBM), and high-performance computing (HPC) applications .

Semiconductor manufacturing has entered the "Foundry 2.0" era, where the deep integration of manufacturing, packaging, and testing has become the new competitive battleground. Industry giants like TSMC, SK Hynix, and Intel are making massive investments in advanced packaging capacity. SK Hynix, for example, is investing $3.87 billion to build a 2.5D packaging production line in the United States, scheduled to begin operations in the second half of 2028 .

The Four Essential Elements of Advanced Packaging

To understand advanced packaging intuitively, imagine these four essential elements as urban infrastructure:

Wafer serves as the city's foundation—the fundamental material on which all chips are built. Just as a solid foundation ensures a city's stability and durability, wafer quality determines chip performance and reliability.

Bump functions like bridges within a city—tiny connection points (typically metallic) that link chips to packaging substrates, enabling smooth information flow between components.

Redistribution Layer (RDL) resembles a city's road network—it reroutes and redistributes signal paths, ensuring seamless communication between different "buildings" (chips).

Through-Silicon Via (TSV) acts like elevators in high-rise buildings—vertical connections through silicon that enable information to travel from down to up layers, dramatically improving data transmission efficiency and reducing signal delay.

These four elements work together to dramatically enhance chip performance and functionality, creating new opportunities for the semiconductor industry. The relationship between them is synergistic: RDL expands circuits in the X-Y plane, TSV enables vertical electrical interconnection along the Z-axis, Bump connects chips to package interfaces, and Wafer serves as the fundamental carrier for integrated circuits.

1. Wafer: The Foundation of Semiconductor Manufacturing

Definition and Role

A wafer is the core substrate material in semiconductor manufacturing—the platform upon which integrated circuits are built. All chip circuitry is processed and formed on these thin silicon slices, with each individual chip (die) being cut from the wafer. Consequently, wafer quality and dimensions directly impact final chip performance and yield.

Historical Evolution

Semiconductor wafer development began in the 1950s using germanium, but silicon quickly became the dominant material due to its superior semiconductor properties, abundant resources, and relative ease of processing. Wafer diameters have continuously expanded as manufacturing processes advanced:

• Historical sizes: 1-inch (25mm), 2-inch (51mm), 3-inch (76mm), 4-inch (100mm)

• Modern standards: 150mm (6-inch), 200mm (8-inch), 300mm (12-inch), with 450mm (17.7-inch) under development

Purity and Quality Requirements

Purity requirements have become increasingly stringent as chip dimensions shrink and integration density rises. Modern wafers are nearly pure silicon with impurity levels typically below one part per billion. Additionally, the crystal structure must be virtually perfect to avoid defects during manufacturing—requiring highly controlled production environments involving single crystal silicon ingot growth, cutting, polishing, and cleaning.

Advanced Wafer Materials

Beyond traditional silicon, compound semiconductor wafers like Gallium Nitride (GaN) and Silicon Carbide (SiC) are gaining prominence for high-frequency and high-power applications including 5G communications, RF components, and electric vehicles. These materials offer superior performance characteristics that silicon cannot match in specific high-end applications .

2. Bump: Bridging Chips and Substrates

Definition and Function

In integrated circuit packaging, bumps are that establish electrical connections and mechanical fixation between chips and packaging substrates. Functioning like bridges, they ensure stable signal transmission while providing necessary physical support.

Historical Development

Bump technology originated in the 1960s when IBM developed the C4 (Controlled Collapse Chip Connection) process, placing tin-lead solder bumps on chip pads and flip-chip bonding to substrates—the foundation of modern bump technology.

Technology Evolution

As electronic products miniaturized and integration increased, bump technology evolved through multiple material and form factor generations:

• Traditional tin-lead alloys replaced by materials (tin-silver-copper alloys)

• Continuous reduction in bump for finer pitches

• Industry moving toward 20μm bump pitch, with leaders achieving <10μm

• For pitches >20μm, thermal compression bonding (TCB) with micro-bumps is employed

• High-density applications now require bump densities approaching 10,000/mm² 

Future Directions

Looking forward, hybrid bonding (HB) copper-to-copper connection technology promises even smaller pitches (<10μm) and higher bump densities, driving simultaneous bandwidth and power efficiency improvements. This technology eliminates traditional solder bumps entirely, using direct copper-to-copper bonding for the ultimate in interconnect density .

3. Redistribution Layer (RDL): The Signal Routing Network

Definition and Function

RDL is a metal layer in chip packaging that redistributes electrical signals, effectively rerouting original chip I/O pads for more efficient connection with packaging substrates or other chips. Think of it as a road network that redistributes I/O pads across larger areas for higher connection efficiency.

Historical Development

This technology first appeared in flip-chip packaging to overcome traditional I/O density limitations. By adding single or multiple metal routing layers on chip surfaces, Early RDL used simple single-layer routing for low pin-count chips, but as semiconductor processes advanced, multilayer structures emerged supporting complex signal transmission and higher densities.

Materials Evolution

Materials evolved correspondingly—from traditional aluminum and copper to advanced combinations including high-conductivity copper with excellent insulating materials like polyimide (PI) or epoxy resins. These material choices directly impact RDL conductivity, mechanical strength, and reliability. Modern RDL structures may include up to ten metal layers in advanced designs .

Wafer-Level Metal Redistribution Process

1. Apply insulating protective layer on IC

2. Define new circuit patterns through photolithography

3. Electroplate new metal traces connecting original chip pads to new bumps

Application in Advanced Packaging

RDL plays crucial roles in both Fan-In Wafer-Level Packaging (FIWLP) and Fan-Out Wafer-Level Packaging (FOWLP). In FIWLP, bumps grow entirely on-chip, with connections relying on RDL metal traces—resulting in package sizes nearly identical to chip dimensions. In FOWLP, bumps can extend beyond chip boundaries, increasing package area by approximately 1.2×.

TSMC's InFO technology exemplifies advanced 2.5D packaging, embedding one or multiple dies in molded compound and fabricating RDL interconnects and dielectric layers on the wafer—demonstrating the "chip-first" process .

4. Through-Silicon Via (TSV): Vertical Connectivity

Definition and Types

TSV technology encompasses both 2.5D TSV (using interposers) and 3D chip stacking. 2.5D TSV employs interposers as platforms connecting multiple chips (processors, memory). Think of it as a multi-layer cake where each layer sits on a porous tray (interposer), with tray holes (TSV) enabling communication between layers.

3D TSV represents direct vertical electrical connections through silicon, primarily for 3D integrated circuits and packaging. This enables direct vertical chip-to-chip connections, overcoming traditional planar routing limitations to achieve higher interconnect, faster signal transmission, and lower power consumption.

The Analogy

Imagine traditional chips as a thick book where pages must exchange information through edges (external interconnects), while TSV creates holes through the book allowing direct page-to-page communication—dramatically, reducing signal delay and power consumption.

Historical Development

TSV concept emerged in the 1980s but gained widespread industry attention in the early 2000s. As Moore's Law progressed , the industry sought vertical integration solutions, with TSV becoming a critical breakthrough.

Manufacturing Challenges and Standards

Despite enormous potential, TSV implementation faces challenges including precise deep etching, thermal stress management, and electrical isolation between vias. To address these challenges systematically, the industry has developed comprehensive standards. In March 2025, China's National Defense Science and Technology Industry Bureau released a seven-part series of standards for "Test Methods for TSV Structures in Integrated Circuit 3D Packaging" (GF/R 435-2025), covering:

• Interface residual stress measurement (X-ray diffraction, nanoindentation)

• Interface bonding strength evaluation

• Filled Cu deformation quantification

• Cu mechanical constitutive properties

• Cu microstructure characterization 

Current Applications

TSV technology has achieved remarkable success in high-performance computing, image sensors, and memory applications. HBM (High Bandwidth Memory) is a prime example, using TSV to stack multiple DRAM dies vertically, achieving bandwidth exceeding 1 TB/s while maintaining compact footprints .

5. 2.5D and 3D Packaging: The Integration Landscape

The Rise of 2.5D Packaging

2.5D packaging has become the core technology supporting AI chip high-performance requirements. It connects multiple chips horizontally through silicon interposers or embedded bridge technologies (such as Intel's EMIB), enabling integration of CPUs, GPUs, memory (HBM), and I/O modules within a single package .

Key 2.5D Technologies:

• TSMC CoWoS (Chip-on-Wafer-on-Substrate): Chips are first connected to silicon wafers through CoW process, then integrated with substrates

• FOCoS (Fan-Out Chip-on-Substrate): Chips placed on RDL interposer surfaces for integration

• FOCoS-Bridge: RDL interposer with embedded bridge structures providing fine-line connections

The silicon interposer size in TSMC's CoWoS technology has evolved from 1.5× reticle size (~1,287mm²) in 2016 to 3.3× (~2,831mm²) currently, supporting 8 HBM3 stacks, with plans to expand to 5.5× (4,719mm²) by 2026 to accommodate 12 HBM4 stacks .

HBM4: Driving Packaging Innovation

The upcoming HBM4 memory standard doubles I/O count to 2,048 signals, increasing bandwidth but also introducing voltage challenges and signal interference risks. SK Hynix is developing new packaging technologies to address these challenges:

• Increasing thickness of upper DRAM chips while narrowing inter-layer spacing

• Developing new mold underfill (MUF) materials capable of filling narrower gaps uniformly

• Maintaining package height of 775μm while improving power efficiency 

3D Packaging: The Next Frontier

3D packaging represents the ultimate goal, with the key benefit being dramatic reduction in interconnect distances. Core technologies include:

• TSV for vertical conductive channels (Samsung X-Cube technology stacks SRAM with logic)

• Hybrid Bonding (TSMC SoIC) with Cu-Cu direct bonding achieving <10μm interconnect pitch

• Bandwidth density reaching 1 TB/s/mm², 10× improvement over traditional micro-bumps 

ASML has already delivered the first "TWINSCAN XT:260" lithography system specifically developed for advanced packaging applications, supporting 3D chip and chiplet manufacturing with 400nm resolution and throughput of 270 wafers per hour .

6. Epoxy Molding Compound (EMC): The Critical Enabling Material

What is EMC?

Epoxy Molding Compound is an indispensable material in electronic packaging, providing exceptional protection and electrical properties. EMC is a thermosetting chemical material for semiconductor encapsulation, based on epoxy resin with high-performance phenolic resin curing agents, fused silica fillers, and various additives .

Core Functions of EMC

• Environmental Protection: Shields semiconductor chips from moisture, temperature variations, and contaminants

• Electrical Insulation: Provides excellent dielectric properties (volume resistivity >10¹⁴ Ω·cm)

• Thermal Management: Facilitates heat dissipation (thermal conductivity ≥0.8 W/m·K)

• Mechanical Support: Protects against physical stress (bonding strength ≥15 MPa)

• Chemical Resistance: Withstands manufacturing and operating environments

Key Performance Parameters

EMC Formulation Components

Epoxy Resin: The primary component providing structural characteristics:

• Ortho-cresol novolac epoxy: High thermal and chemical stability

• Bisphenol A epoxy: Low shrinkage and low volatile content

• Multifunctional epoxy: High Tg and fast curing

• Biphenyl epoxy: Low viscosity, high filler loading capability

• Naphthalene-type epoxy: High Tg, excellent heat resistance

• Modified epoxy: Enhanced flexibility 

Hardener (Curing Agent): Reacts with epoxy to form stable three-dimensional networks. Phenolic resins are most common.

Silica Fillers: Available in crystalline, fused, and spherical forms. Filler content can reach 90 wt% in advanced formulations, significantly reducing CTE and improving thermal conductivity .

Additives: Curing accelerators, coupling agents, flame retardants, colorants, and modifiers fine-tune specific properties.

EMC Classification by Application

Environmental Compliance

With global regulations like EU WEEE and RoHS, the industry has shifted from traditional brominated/antimony EMC to green EMC (halogen-free, antimony-free). This transition requires:

• New eco-friendly flame retardants (metal hydroxides, borates)

• Self-extinguishing resin systems

• Higher filler loading to achieve flame retardancy 

Choosing the Right Epoxy for Your Application

With the rapid evolution of packaging architectures—from traditional lead-frame packages to advanced 2.5D/3D integrations—selecting the appropriate epoxy molding compound has become increasingly complex. Engineers must balance multiple competing requirements:

• Thermal performance vs. mechanical stress

• Flowability for fine-pitch applications vs. filler loading for low CTE

• Cure speed for manufacturing efficiency vs. material stability

• Cost vs. reliability for target applications

For detailed guidance on selecting the optimal epoxy formulation for your specific packaging requirements—including comprehensive technical specifications, comparative performance data, and application recommendations—we invite you to explore our dedicated resource:

👉 What is Electronic Encapsulation Epoxy Adhesive? – Every Engineer Should Know

This comprehensive guide covers:

• Complete breakdown of epoxy resin chemistry and formulation principles

• Detailed comparison of one-component vs. two-component systems

• Selection criteria for different packaging types and reliability requirements

• Thermal management strategies and material optimization techniques

• Industry standards compliance and qualification testing

7. Advanced EMC Technologies for Next-Generation Packaging

Liquid Compression Mold Underfill (LCMUF)

Traditional 2.5D packaging requires separate underfill and overmolding steps. LCMUF technology enables one-step underfill and molding simultaneously, simplifying processing and improving throughput.

NAMICS has developed LCMUF materials with:

• Flexible resin systems reducing modulus and warpage

• Optimized filler particle size distribution for narrow gap flow

• 12-inch wafer warpage reduced to 510μm with excellent molding quality 

Liquid Molding Compound (LMC) and Sheet Molding Compound (SMC)

LMC enables compression molding for wafer-level packaging with reduced thickness. However, flow marks become problematic at very thin thicknesses. Nagase has developed SMC (Sheet Molding Compound) to address this challenge:

• Eliminates flow marks by using sheet form rather than liquid flow

• Enables further thickness reduction without compromising quality

• Better warpage control for large-panel applications 

High Thermal Conductivity, Low Loss Materials

For high-speed computing applications, ITRI has developed novel materials featuring:

• Multifunctional low-polarity resins (reducing dielectric loss at high frequencies)

• Thermal filler loading up to 90 wt%

• Tg = 190.4℃, CTE = 11.5 ppm/℃ before Tg

• Thermal conductivity = 2.17 W/m·K

• Dielectric loss Df = 0.002 at 60 GHz

• 12-inch wafer warpage = 0.827 mm 

Reliability Considerations for Green EMC

When selecting environmentally friendly EMC, engineers must carefully evaluate:

Moisture Resistance: Moisture penetration occurs through the EMC body or along interfaces with leadframes. High purity (minimizing Na+, Cl- ions) and strong filler-resin bonding are essential. Pressure Cooker Testing (PCT) at 121℃, 29.7 psi for 96+ hours validates moisture resistance .

Adhesion: Green EMC formulations may use different resin systems affecting adhesion to various leadframe platings (Cu vs. Ag). Self-extinguishing resins often have lower viscosity, requiring mold release agents that can reduce adhesion and increase delamination risk .

Internal Stress: CTE mismatch between EMC (20-26×10⁻⁶/℃) and silicon/leadframe (~16×10⁻⁶/℃) creates internal stress during cooling. Temperature Cycling (TC) testing from -55℃ to 150℃ for 500-1000 cycles validates stress resistance .

8. Market Trends and Domestic Progress

Global Market Outlook

According to QYResearch, the global semiconductor EMC market is projected to grow from $2.097 billion in 2022 to $3.170 billion by 2029, representing a CAGR of 4.7% . This growth is driven by:

• Increasing semiconductor content across all electronics

• Rising demand for advanced packaging solutions

• 5G, AI, and IoT driving higher performance requirements

• Electric vehicles and renewable energy systems

• Continuous innovation in packaging architectures

Domestic Advanced Packaging Capabilities

Chinese OSATs have made significant progress in advanced packaging:

SJ Semiconductor : The first company in Mainland China to achieve volume production of 12-inch wafer bumping and 14nm advanced process bumping services. With approximately 85% revenue share in China's 2.5D packaging market (2024), their technical capabilities show no generation gap with global leaders .

JCET : The XDFOI high-density fan-out packaging platform supports 2.5D packaging for 4nm node chiplet products, using multi-layer RDL routing and micro-bump technology for applications in mobile terminals and edge AI .

Tongfu Microelectronics : Achieved breakthroughs in 2.5D/3D packaging through collaboration with AMD, with TSV process costs 40% lower than overseas competitors and HBM technology co-development .

2026 Outlook: A Strong Cycle for Advanced Packaging

According to brokerage reports, 2026 is expected to be an acceleration year for advanced packaging, characterized by:

• Highly determined demand combined with supply-side expansion

• Tight supply-demand balance sustained by AI traction

• Rising value contribution (single-chip packaging+test costs approaching or approaching wafer manufacturing costs)

• Storage packaging entering a "seller's market" with price increases approaching 30% 

9. Emerging Technologies: Glass Substrates and TGV

The Promise of Glass

Glass substrates offer compelling advantages over silicon interposers:

• Larger achievable package sizes

• Better electrical performance (reduced transmission loss)

• Superior warpage resistance

However, glass is brittle and presents unique challenges. Through-Glass Via (TGV) technology is critical to enabling glass substrates .

Remaining Challenges

Glass presents several technical hurdles:

• CTE mismatch with copper causing interface stress

• Brittle nature susceptible to cracking during thermal cycling

• Adhesion issues with smooth glass surfaces

• Processing-induced defects (micro-cracks, stress concentrations) 

Conclusion: Partner with Assembtek for Advanced Packaging Solutions

Advanced packaging represents the future of semiconductor technology, enabling continued performance scaling beyond traditional Moore's Law. The four essential elements—Wafer, Bump, RDL, and TSV—work in concert with high-performance Epoxy Molding Compounds to deliver:

• Miniaturization enabling smaller, more portable devices

• Performance meeting demanding computing requirements (AI, HPC)

• Reliability ensuring long-term functionality (15+ year automotive, server-grade)

• Cost-effectiveness through optimized manufacturing

As the industry saying goes: "One generation of packaging, one generation of materials." The rapid evolution of packaging architectures demands equally rapid innovation in material systems. Epoxy Molding Compounds must continuously advance to meet increasingly stringent requirements for:

• Lower warpage for large packages (sub-500μm for 12-inch wafers)

• Smaller filler particles for fine-pitch applications (<10μm for HBM stacks)

• Higher thermal conductivity for power density (>2 W/m·K)

• Improved adhesion for heterogeneous integration

• Faster cure cycles for manufacturing efficiency

• Environmental compliance (halogen-free, RoHS)

At Assembtek, we understand that every advanced packaging application presents unique challenges. Our technical team possesses deep expertise in semiconductor materials and can guide you through the selection process—from initial material qualification through process optimization and reliability testing.

Ready to ensure your advanced packaging designs meet the highest standards for performance and reliability?

📞 Contact our semiconductor materials specialists today for expert guidance on selecting the optimal epoxy molding compound for your application.
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Visit Assembtek.com to discover how our engineered material solutions can improve the performance, reliability, and manufacturability of your advanced semiconductor packages!